Parasitic Capacitance
=====================

Parasitic capacitance checks reveal unwanted coupling paths, loading, frequency
                shifts, and edge-field concentration.

.. list-table::
   :header-rows: 1

   * - #
     - Parameter
     - Symbol / Unit
     - Extraction Method
     - Typical Q3D Value
     - Ideal / Optimal
     - Good Range
     - Worst Case
     - Why It Matters
     - Key Design Note
   * - 29
     - Trace-to-Ground Parasitic Cap
     - C_trace / fF/μm
     - Q3D electrostatic solve per-unit-length
     - 0.1 – 0.4 fF/μm
     - 0.1 – 0.4 fF/μm (50 Ω CPW)
     - 0.1 – 1 fF/μm
     - > 3 fF/μm
     - Distributed capacitance sets CPW characteristic impedance Z_0 = √(L/C);
                        target 50 Ω
     - C' depends on gap width and substrate thickness; narrowing the gap increases
                        C' (lowers Z_0)
   * - 30
     - Pad-to-Substrate Parasitic Cap
     - C_sub / fF
     - Q3D C matrix with substrate dielectric stack
     - < 10 fF
     - < 10 fF (small contact pads)
     - 5 – 30 fF
     - > 100 fF
     - Substrate capacitance creates parasitic shunt path reducing resonator Q and
                        shifting qubit freq
     - Thinning substrate from 500 μm to 200 μm reduces C_sub by ~2.5×; used in 3D
                        chip stacks
   * - 31
     - Inter-Layer Cap (3D integration)
     - C_layer / fF
     - Q3D 3D stack model; bump height geometry sweep
     - < 5 fF per crossing
     - < 5 fF (flip-chip bump)
     - 1 – 20 fF
     - > 50 fF
     - Capacitance between chip layers through indium/SnAg bumps must be included
                        in Hamiltonian
     - Bump height variation (σ ~ 1–2 μm) causes C_layer spread of ~0.5–1 fF;
                        matters at scale
   * - 32
     - Fringe Capacitance (gap edges)
     - C_fringe / fF/μm
     - Q3D conformal mesh at conductor edges
     - 0.02 – 0.1 fF/μm
     - 0.02 – 0.1 fF/μm (5–20 μm gap)
     - 0.05 – 0.5 fF/μm
     - > 1 fF/μm
     - Fringe fields at edges add to intended coupling capacitance; must be in C_g
                        design model
     - ~30–50% of C_g in typical transmon designs comes from fringe;
                        underestimating shifts f by 50+ MHz
   * - 33
     - Wirebond Pad Parasitic Cap
     - C_pad\_wb / fF
     - Q3D parallel-plate + fringe approximation; or analytical C = ε₀ εr A/d
     - < 50 fF (100×100 μm Al pad)
     - < 50 fF
     - 20 – 150 fF
     - > 300 fF
     - Bond-pad capacitance loads the signal line; degrades bandwidth and causes
                        reflection at bond
     - Reducing pad size from 150×150 μm to 80×80 μm cuts C_pad by ~2.5× with no
                        bond yield penalty