Substrate & Dielectric Loss
===============================

Substrate and dielectric-loss outputs explain how material selection and surface
                participation affect T_1.

.. list-table::
   :header-rows: 1

   * - #
     - Parameter
     - Symbol / Unit
     - Extraction Method
     - Typical Q3D Value
     - Ideal / Optimal
     - Good Range
     - Worst Case
     - Why It Matters
     - Key Design Note
   * - 40
     - Substrate Bulk Loss Tangent
     - tan delta_bulk
     - Q3D dielectric loss tangent input; resonator Q fitting vs power
     - < 10⁻⁶ (HR-Si, 4K)
     - < 10⁻⁶
     - 10⁻⁶ – 10⁻⁵
     - > 10⁻⁴
     - Bulk dielectric loss sets floor on 1/Q_int from substrate volume; sapphire 
                        < 5×10⁻⁷
     - tan δ improves by 10–100× on cooling from 300K to 4K due to reduced phonon
                        and TLS population
   * - 41
     - Metal-Air Interface Loss (tan delta_MA)
     - tan delta_MA
     - Surface participation ratio (SPR) from Q3D E-field + measured Q factor
     - ~10⁻³
     - < 10⁻³ (passivated Al₂O₃)
     - 10⁻³ – 5×10⁻³
     - > 10⁻²
     - TLS loss at metal-air interface is the dominant T₁ source in planar transmon
                        designs
     - Etching native oxide before Al deposition reduces tan delta_MA by up to 10×;
                        HF vapor clean
   * - 42
     - Substrate-Air Interface Loss (tan delta_SA)
     - tan delta_SA
     - SPR analysis from Q3D E-field distribution
     - ~5×10⁻⁴
     - < 5×10⁻⁴ (HF-etched Si)
     - 5×10⁻⁴ – 5×10⁻³
     - > 10⁻²
     - TLS at substrate exposed surface; addressed by passivation, UV ozone clean,
                        or dry etching
     - Hydrogen-passivated Si surface (HF dip) shows 5× lower tan delta_SA vs
                        untreated Si
   * - 43
     - Metal-Substrate Interface Loss (tan delta_MS)
     - tan delta_MS
     - EELS/TEM interface composition + Q3D SPR calculation
     - ~5×10⁻³
     - < 5×10⁻³
     - 5×10⁻³ – 10⁻²
     - > 5×10⁻²
     - TLS at Al–Si or Nb–Si interface; reduced by HF dip substrate prep before
                        metal deposition
     - Amorphous interfacial SiOx layer of 1–2 nm is the primary TLS host;
                        substrate HF clean removes it
   * - 44
     - Surface Participation Ratio (SPR)
     - p_MA / ppm
     - Q3D E-field energy integral on metal-air interface: p = ∫_MA ε\|E\|²dV / ∫_all
                        ε\|E\|²dV
     - 5 – 50 ppm
     - < 5 ppm
     - 5 – 50 ppm
     - > 200 ppm
     - p × tan δ contributes directly to 1/Q; minimise by thick metal, wider gap,
                        no sharp corners. For planar transmons, p_MA can reach 100–1000 ppm without
                        geometry optimisation.
     - 1/Q_TLS = Σ p_i × tan δ_i; SPR is the design lever; tan δ is the material
                        lever. <5 ppm ideal is achievable in optimised 3D cavity or large-gap
                        planar designs; planar CPW without optimisation may be 100–1000 ppm.