Verification & Fault Tolerance

To ensure your quantum chip design will function correctly and resist errors, you must run Design Rule Checks (DRC) and analyze its fault tolerance limits.

Design Rule Checks (DRC) and Verification

  1. Open the Verification page.

  2. Click the Run Verification button. The system will check the chip against physical and mechanical design rules.

  3. Review the Verification Report containing: * DRC Violations: Spacing issues, component overlaps, or size limit breaches. * Frequency Collisions: Warnings if two connected qubits are tuned to the same frequency, which causes signal interference. * Severity Flags: * Error (Red): Serious problems that prevent fabrication or execution (for example, overlapping metal). * Warning (Orange): Risks that could cause errors but do not stop execution (for example, tight spacing). * Info (Blue): General recommendations or optimization tips.

  4. Click on the History tab to see past reports and track how many errors you have resolved.

What you just did: You ran a quality check on the chip layout, making sure the design fits the physical limits of the manufacturing equipment.

Fault Tolerance Studio

The Fault Tolerance Studio calculates if the processor’s physical properties are sufficient to build reliable logical qubits.

  1. Navigate to the Fault Tolerance page.

  2. Review the Physics Report Summary sourced from simulation runs: * Coherence Times (T1/T2): How long qubits can store quantum information before it leaks (higher values are better). * Dispersive Shifts (χ): The coupling strength between qubits and readout resonators. * Purcell Limit: The maximum lifetime of a qubit when connected to a readout resonator.

  3. Review the calculated Gate Fidelities: * 1-Qubit Gate Fidelity: The accuracy of operations on a single qubit. * 2-Qubit Gate Fidelity: The accuracy of operations linking two qubits. * Readout Fidelity: The accuracy of measuring the qubit states.

  4. Check the Fault Tolerance Threshold Check: Displays whether the average physical error rate is low enough to successfully implement quantum error correction (QEC).

What this means: If your gate fidelities exceed the QEC threshold, you can combine many physical qubits together to form highly stable logical qubits.

Cross-References

To understand how these metrics are calculated from raw simulation data, consult the following technical guides: