Parasitic Inductance

Parasitic inductance checks identify wirebond, via, loop, and package effects that

shift mode frequencies and add crosstalk.

#	Parameter	Symbol / Unit	Extraction Method	Typical Q3D Value	Ideal / Optimal	Good Range	Worst Case	Why It Matters	Key Design Note
25	Wirebond / Bump Inductance	L_wb / nH	Q3D wire cylinder model; HFSS S-parameter fitting	0.5 – 2 nH per bond	< 1 nH	0.3 – 3 nH	> 5 nH	Series inductance in signal path creates impedance discontinuity; resonates near operating freq	Flip-chip indium bumps reduce L_wb to ~0.1 nH vs 1–2 nH for wirebonds; key for 3D scaling
26	Control Line Lead Inductance	L_lead / pH	Q3D PEEC; partial inductance extraction	< 100 pH	< 100 pH (short on-chip)	50 – 500 pH	> 2 nH	Lead inductance in flux/charge bias lines causes AC flux errors and qubit frequency shifts	Long coax from room-temperature electronics adds 1–10 nH; de-embed by careful calibration
27	Ground Plane Slot Inductance	L_slot / pH/sq	Q3D mesh simulation of ground plane geometry	< 1 pH/sq	< 1 pH/sq (continuous ground)	1 – 5 pH/sq	> 20 pH/sq	Inductance from ground return path gaps distorts mode frequencies across the chip	Vortex-pinning holes (diameter ~ 1 μm, pitch ~ 2 μm) add ~5–10 pH/sq but are necessary at B > 0
28	Package / Board Parasitic Inductance	L_pkg / nH	HFSS full package model + Q3D trace extraction	< 0.5 nH (SMA launch)	< 0.5 nH	0.5 – 2 nH	> 5 nH	Package inductance shifts resonator input impedance; must be de-embedded from measurement	Surface-mount SMP connectors (< 0.3 nH) preferred over SMA (~0.5–1 nH) for cryo packages